The present invention is directed, in general, to semiconductor manufacturing and, more specifically, to a method for capping high aspect ratio metal features in integrated circuit fabrication.
It has recently become desirable to incorporate inductors into sub-micron integrated circuit devices. In the fabrication of such integrated circuits, the inductor is typically formed at the final metal level, the metal layer is much thicker, e.g., 3000 nm, than the standard metal layers, e.g., 500 nm, that serve as device interconnects. Thicker metal layers, e.g., aluminum, are used for the inductor level because higher inductance can be achieved with the thicker metal. Of course, metals other than aluminum, such as copper, etc., may also be used in the future.
As inter-device distances are forced ever smaller, because of market pressures to make faster integrated circuits, these thicker metal layers result in features with a high aspect ratio with respect to inter-device distances. For example, with a feature as thick as 3000 nm the inter-device distance may be as small as 2000 nm. As is customary before final encapsulation, these metal features must be covered with a capping material, often comprising silicon dioxide (SiO2) and silicon nitride (SiN) layers. The coverage of the SiN layer is especially important because a continuous layer is needed on both horizontal and vertical surfaces of the metal features to prevent moisture from penetrating the device and corroding the metal. Of course, the deposition of the capping layer must result in a low compressive stress to avoid stress migration or electromigration.
Conventional capping methods for metal features use a high density plasma (HDP) oxide deposition followed by a plasma enhanced chemical vapor deposition (PECVD) of SiN. One who is skilled in the art recognizes that HDP and PECVD processes result in markedly different deposition profiles. Referring initially to FIG. 1, illustrated is a partial sectional view of a simplified conventional integrated circuit 100 having thick metal features 110, 120 atop an intermediate dielectric layer 130, an oxide layer 140 deposited by HDP and a nitride layer 150. The thick metal features 110, 120 may also be referred to as high aspect ratio features 110, 120. During deposition, the HDP oxide 140 deposits sufficiently in the space or trench 160 between adjacent thick metal features 110, 120 at a thickness 145 approximately equal to a thickness 115 of the HDP oxide atop the thick metal features 110, 120. However, the HDP oxide 140 is not conformal to the semiconductor topography, but deposits as shown, and therefore provides relatively little coverage of near-vertical surfaces 112, 122 and shoulders 113, 123 of the high aspect ratio features 110, 120, respectively. The SiN layer 150 is shown as it would be deposited by a PECVD process over the oxide layer 140.
It should be understood that it is highly desirable to have as much of the trench 160 filled by dielectric material before the integrated circuit 100 is subjected to a final packaging step. During packaging, a molding compound (not shown) is injected under pressure to fill any remaining voids and could induce stresses in the thick metal features 110, 120. Variation in trench 160 fill or dielectric properties caused by molding packaging would have adverse effects on the electrical performance of circuits using thick metal inductors. With the HDP deposition as shown in FIG. 1, the oxide layer 140 coverage over shoulders 113, 123 would be of an inadequate thickness 114, 124, respectively, while adequately filling the trench 160. One effort to resolve this problem attempted to deposit up to 3000 nm of oxide 140 over thick metal features 110, 120 of 3000 nm height so as to completely fill the trench 160. This resulted in stresses so great that the wafer (not shown) was severely warped, and the integrated circuits unuseable.
Referring now to FIGS. 2A and 2B, illustrated are partial sectional views of a simplified conventional integrated circuit 200 having thick metal features 210, 220 atop an intermediate dielectric layer 230, an oxide layer 240 deposited by PECVD, and a nitride layer 250. Deposition of the oxide layer 240 by PECVD results in a xe2x80x9cmushroomingxe2x80x9d of the oxide around the thick metal features 210, 220. In some extreme cases, reentrant surfaces 243 (FIG. 2A) or even voids 245 (FIG. 2B) may form. Of course, manufacturing defects such as these are unacceptable. The subsequent capping layer 250 of SiN would be formed as shown. Therefore, referring to both FIGS. 1 and 2, it is clear that neither HDP nor PECVD deposition of the oxide layer 130, 230, respectively, forms a satisfactory basis for the capping layer 150, 250.
Accordingly, what is needed in the art is a method of forming an oxide/nitride capping layer over high aspect ratio metal features that assures adequate oxide and nitride thicknesses, especially over the feature shoulders.
To address the above-discussed deficiencies of the prior art, the present invention provides a method of manufacturing an integrated circuit having a capping layer over a thick metal feature. In one embodiment, the method comprises forming first and second oxide layers over the thick metal feature, forming a composite oxide layer including an oxide spacer by etching the first and second oxide layers, and forming a capping layer over the composite oxide layer. More specifically, forming the first oxide layer involves using a high density plasma (HDP) process, forming the second oxide layer involves using a plasma enhanced chemical vapor deposition (PECVD) process, and forming the composite oxide layer preferably includes etching with a reactive ion etch.
Thus, in a broad sense, the present invention provides a method for forming a spacer of an oxide so that a greater thickness of oxide smooths the transition from an upper surface of a thick metal feature to the side of the thick metal feature. The formation of the spacer facilitates formation of a capping layer over the oxide layer.
In another embodiment, the method includes forming the first oxide layer using an HDP process having a first deposition-to-sputter ratio. In one particular aspect of this particular embodiment, the method includes forming a first oxide layer using a first deposition-to-sputter ratio of about 4.5. Further, the method may comprise forming a third oxide layer on the first oxide layer prior to forming the second oxide layer. The formation of the third oxide layer may employ a second HDP process having a second deposition-to-sputter ratio. In a specific aspect of this embodiment, the method includes using an HDP process with a second deposition-to-sputter ratio of about 7.0. In other embodiments, the method includes forming first and third oxide layers of about 400 nm thickness.
The method, in yet another embodiment, includes forming a second oxide layer from a gas mixture including tetraethylorthosilicate and oxygen at a temperature ranging from about 250xc2x0 C. to about 400xc2x0 C. The process pressure may range from about 0.1 Torr to about 10 Torr and high frequency radiation may be applied ranging from about 200 kHz to about 13.56 MHz with a power ranging from about 100 Watts to about 2000 Watts. In a more specific aspect, the method includes forming a second oxide layer at a temperature of about 350xc2x0 C., a pressure of about 4.0 Torr, and high frequency radiation of about 13.56 MHz with a power of about 1200 watts. The method may further include forming an oxide spacer having a base thickness ranging from about 40 percent to 60 percent of the thickness of the composite oxide layer. In a preferred aspect, the method includes forming an oxide spacer having a base thickness of about 50 percent of the thickness of the composite oxide layer.
In another embodiment, the method includes reactive ion etching with a gas mixture of trifluoromethane ranging from about 10 sccm to about 50 sccm, carbon tetrafluoride ranging from about 10 sccm to about 50 sccm, and argon ranging from about 50 sccm to about 250 sccm. The process pressure may range from about 50 mTorr to about 200 mTorr with power ranging from about 600 Watts to about 1200 Watts, and a magnetic field ranging from about 0 Gauss to about 40 Gauss. In a specific aspect, the method includes etching with a gas mixture of trifluoromethane at about 30 sccm, carbon tetrafluoride at about 30 sccm, and argon at about 60 sccm. The process pressure may be about 160 mTorr with a power of about 900 Watts, and a magnetic field of about 20 Gauss.
The method may further include forming the capping layer of silicon nitride using a PECVD process. In yet another embodiment, the method includes forming a second oxide layer having a refractive index of about 1.465 at xcex=633 nm. In a further aspect, the method may include a thick metal feature of about 3000 nm thickness.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.